Samsung Electronics Unveils 3D Stacked Transistor Technology

Samsung Electronics has succeeded in implementing the industry's smallest three-dimensional (3D) stacked field-effect transistor (FET). The research team applied a structure that stacks transistors vertically to increase integration density, achieving an industry-leading gate pitch of 42 nanometers.

This research was highly acclaimed, selected as a best paper among over 1,000 submissions. The technology holds significant importance, particularly as it was applied to logic semiconductors that perform computation and control functions.

Samsung Electronics projects that this technology could lead to a doubling of power efficiency and up to a 100% improvement in performance. This is evaluated as suitable for next-generation logic semiconductors, as it allows for more computations to be processed with lower power consumption in a smaller area.