Huawei to roll out two AI chips next year
Huawei will release two AI semiconductor products from its 'Ascend 960' series in the first and third quarters of next year. Wang Tao, Huawei's rotating chairman, announced the launch plan for the 'Ascend 960' AI chip series at Huawei Connect 2026 in Shanghai on the 17th. Among the Ascend 960 series, the 960DT is set to launch in the first quarter of next year, followed by the 960PR in the third quarter. Wang said the Ascend 960 delivers double the performance of its predecessor.
Huawei said it will evolve the Ascend chips one generation per year, releasing the 'Ascend 970' in 2028 and the 'Ascend 980' in 2029, while continuously boosting computing power, memory capacity, and inter-chip transfer speeds. At the same event last year, Huawei unveiled a roadmap to release a new AI chip annually over the next three years, doubling computing power each time.
Huawei's technology development goes beyond individual chips to focus on systems. The company is developing 'UnifiedBus', an interconnect technology that allows multiple AI chips to exchange data rapidly and operate as a single computing system. Wang said 11 types of semiconductors leveraging UnifiedBus have been developed. In large-scale AI systems called 'superclusters' built on this technology, up to 1 million AI processors can be linked together.
Huawei also said it has deployed more than 1,000 sets of the 'Atlas 950 SuperPoD', an AI computing system smaller than a supercluster, supplying over 370 customers as large-scale commercialization begins. The next-generation 'Atlas 960 SuperPoD', the first in the industry to apply near-package optics (NPO), is planned for release in the third quarter of next year.
US export controls form the backdrop of this push. The announcement came as US semiconductor restrictions on China have made it difficult for Chinese companies to secure enough of Nvidia's latest AI chips. Huawei has shifted to a 'computing system' strategy that competes on how many domestic chips it can bundle together and how fast, rather than on individual chip performance.
